1. Field of the Invention
The present invention relates to a filter including common mode feedback that provides single-ended to differential-ended conversion with minimum loss of performance.
2. Related Art
Differential topologies for integrated circuit (IC) analog signal processing offer numerous advantages, e.g. robustness to crosstalk and improved linearity. However, many source signals, such as video signals, are only available in single-ended format and therefore must be converted to differential format before processing begins.
The conversion to differential format can be done efficiently on an analog-to-digital conversion (ADC) input stage implemented with switched-capacitors. However, in many applications, an anti-aliasing filter must precede the ADC. In such applications, a single-ended-to-differential (SE-to-DE) conversion is typically done before the filter to retain the advantages of improved linearity and robustness to crosstalk.
Several solutions exist to provide this SE-to-DE conversion, each with its own drawbacks. In one solution, one relies on the common mode feedback (CMFB) of the differential amplifier used on the first stage of the filter that, by feedback, forces its output to be differential. FIG. 1 illustrates this solution.
As shown in FIG. 1, a filter 100 essentially reconstructs the differential format at the output. In the embodiment shown in FIG. 1, filter 100 includes a first path that serially connects a differential voltage input terminal VI+, a buffer 101A, a resistor R1A, and an RC circuit comprising a resistor R2A, a capacitor CA connected in parallel, and a differential voltage output terminal VO−. Filter 100 also includes a second path that serially connects a differential voltage input terminal VI−, a buffer 101B, a resistor R1B, an RC circuit comprising a resistor R2B and a capacitor CB connected in parallel, and a differential voltage output terminal VO+. Note that although filter 100 includes both differential voltage input terminal VI+ and VI−, differential voltage input terminal VI− receives a DC signal and therefore filter 100 is technically a single-ended input.
To provide the above-described reconstruction, a differential amplifier 102 is connected to the two RC circuits. Specifically, a first terminal of resistor R2A (i.e. that terminal connected to resistor R1A) is connected to a positive input terminal of differential amplifier 102, a first terminal of resistor R2B (i.e. that terminal connected to resistor R1B) is connected to a negative input terminal of differential amplifier 102, a second terminal of resistor R2A (i.e. that terminal connected to differential voltage output terminal VO−) is connected to a negative output terminal of differential amplifier 102, and a second terminal of resistor R2B (i.e. that terminal connected to differential voltage output terminal VO+) is connected to a positive output terminal of differential amplifier 102. Note that differential amplifier 102 receives a common mode signal at terminal VCMO.
Filter 100 can minimize consumption and area because it re-uses hardware that is already present in the differential filter topology. However, filter 100 does not retain the advantages of differential processing because the virtual ground has a common mode signal swing, thereby leading to poor linearity (especially if switches are used in the signal path for programming).
FIG. 2 illustrates another filter 200 that can provide SE-to-DE conversion. In this embodiment, filter 200 includes operational amplifiers 201A, 201B, and 201C. The negative input terminals of operational amplifiers 201A and 201B are connected to the differential input terminal VI+, whereas the negative input terminal of operational amplifiers 201C is connected to the differential input terminal VI− (this terminal receiving a DC signal). Resistors r1-r4 are serially connected between the output terminals of operational amplifiers 201A and 201C. A node between resistors r1 and r2 is connected to the positive input terminal of operational amplifier 201A, a node between resistors r2 and r3 is connected to the output terminal of operational amplifier 201B, and a node between resistors r3 and r4 is connected to the positive input terminal of operational amplifier 201C.
Filter 200 further includes a resistor RA connected between the output terminal of operational amplifier 201A and an RC circuit comprising a capacitor CA and a resistor RA/2 (wherein RA/2 also designates the relative value based on resistor RA), which are connected in parallel. A resistor RB connected between the output terminal of operational amplifier 201C and an RC circuit comprising a capacitor CB and a resistor RB/2 (wherein RB/2 also designates the relative value based on resistor RB), which are connected in parallel. A differential amplifier 202 is connected to the RC circuits. Specifically, a positive input terminal of differential amplifier 202 is connected to a node between resistors RA and RA/2, a negative input terminal of differential amplifier 202 is connected to a node between resistors RB and RB/2, a positive output terminal of differential amplifier 202 is connected to the positive output terminal VO+, and a negative output terminal of differential amplifier 202 is connected to the negative output terminal VO− of differential amplifier 202. Note that differential amplifier 202 outputs a common mode signal at terminal VCMO.
In this configuration, filter 200 effectively has the SE-to-DE stage before the filter stage (circuit around 202). This solution provides the above-described advantages of differential processing, but undesirably increases area and energy consumption (compared to filter 100) for the SE-to-DE converter by including operational amplifiers 201A, 201B, and 201C.
Therefore, a need arises for an SE-to-DE stage in a filter that provides such advantages with minimal area and energy consumption.